A prior art ECL to TTL translator circuit is illustrated in FIG. 1. Differential ECL input signals at the ECL differential inputs V.sub.IN, V.sub.IN are translated to single ended TTL output signals at the single ended TTL output V.sub.OUT. Translation is achieved using a current mirror circuit QB,QA coupled between an ECL input gate Q1,Q2,R1,R2,I0 and a TTL output gate Q9,PULLUP,QLOP, R6,R7. The differential ECL input signals control the conducting states of ECL gate transistor elements Q1,Q2 in opposite phase. Tail current generated by current sink IO passes alternately through the Q1,Q2 collector paths and swing resistors R1,R2 respectively coupled to the high potential power rail V.sub.CC. Collector nodes A,B provide differential ECL output nodes coupled to first and second emitter follower output transistor elements Q7,Q3.
The first emitter follower transistor element Q7 provides a first emitter follower output circuit or network incorporating a first stack of voltage drop components Q8,R4,QB. Base collector shorted (BCS) transistor element QB provides the first branch or master branch of the current mirror circuit. The second emitter follower transistor element Q3 provides a second emitter follower output circuit or network incorporating a second stack of voltage drop components Q4,R3,D3 defining a switching control node D, and current sink transistor element QA. Current sinking transistor element QA is coupled in current mirror configuration with BCS transistor element QB and provides the second branch or slave branch of the current mirror.
Switching control node D in the second emitter follower output circuit is coupled to the base node of TTL gate phase splitter transistor element Q9. Current mirror current sink transistor element QA and the first and second emitter follower output circuits effect the translation by controlling the conducting state of phase splitter transistor element Q9 at switching control node D.
With an ECL low potential level signal at the input V.sub.IN, ECL gate transistor element Q2 is off, and the base node B of the second emitter follower transistor element Q3 is pulled up to the high potential rail V.sub.CC. Q3 conducts and the second emitter follower output circuit component elements Q3,Q4,R3 pullup the switching control node D at the base of phase splitter transistor element Q9. With Q9 conducting, a TTL low potential signal appears at the output V.sub.OUT.
At the same time, ECL gate transistor element Q1 is on pulling down the potential at the base node A of the first emitter follower transistor element Q7. The current in the first emitter follower output circuit and current mirror master branch transistor element QB is at its lowest magnitude. Current sink transistor element QA mirrors this lower magnitude current. Resistor element R5 is a bleed resistor across the base and emitter nodes of QA.
With an ECL high potential level signal at input V.sub.IN, ECL gate transistor element Q2 is on, pulling down the base node B of emitter follower output transistor element Q3. The second emitter follower output circuit components Q3,Q4,R3 no longer pull up the switching control node D. With a high potential level at the base node A of first emitter follower transistor element Q7, the current in the first emitter follower output circuit is at its highest magnitude. The larger current in master branch transistor element QB is reflected in current mirror transistor element QA with a larger sinking current. The base node D of phase splitter transistor element Q9 is pulled low and a TTL high potential level signal appears at the output V.sub.OUT.
A disadvantage of the prior art ECL to TTL translator circuit of FIG. 1 is that current sink transistor element QA takes some of the sourcing current from the second emitter follower output circuit components slowing the turn on of phase splitter transistor element Q9. Furthermore, during turn off of the phase splitter Q9, the sinking current through current sink transistor element QA is limited by the current mirror current set by QB. The current mirror translator limits speed of translation and the switching speed or slew rate at the output.